1. Field of the Invention
The present invention relates to a circuit layout of a flat display panel, and in particular to an interconnect structure for peripheral circuits on a thin film transistor (TFT) array substrate for a flat display panel.
2. Description of the Related Art
Currently, flat panel displays are widely used in various applications with liquid crystal displays (LCDs) a popular choice. A typical TFT-LCD panel comprises an upper and a lower substrate with liquid crystal materials filled therebetween. The upper substrate (in cross-section) is typically known as a color filter substrate and the lower substrate an array substrate having thin film transistors (TFTs) fabricated thereon. A backlight unit is located at the back of the panel. When voltage is applied to a transistor, the alignment of the liquid crystal is altered, allowing light to pass through to form a pixel. The front substrate, i.e. the color filter substrate, gives each pixel its own color. The combination of these pixels in different colors forms images on the panel.
In addition to the TFT array formed on the display area, peripheral circuits are also disposed on the non-display area of the lower substrate, such as driving circuits, scanning circuits and electrostatic discharge (ESD) protection circuits. In the production process of a TFT-array substrate, it is important to effectively protect thin film transistors from damaged by electrostatic charges, thus ESD protection circuits are generally formed on the non-display area to discharge electrostatic charges induced in the circuits during TFTs fabrication.
FIG. 1 is a top view of part of a peripheral circuit for ESD protection in a non-display area of a TFT array substrate. Three parallel metal lines 110, e.g. gate metal lines, opposite to three parallel metal lines 130, e.g. source/drain metal lines, are disposed on the non-display area of a TFT array substrate 100. Each metal line 110 is bridged to the opposite metal line 130, utilizing ITO layers 162 as the wirings. Two passivation layers 151 and 152, parallel to each other, are disposed on opposite sides of the bridging regions, with a trench therebetween exposing the ITO wirings 162.
FIGS. 2A to 2E are cross-sections of FIG. 1 along line 1-1, showing the process for connecting one set of corresponding metal lines 110 and 130. As shown in FIG. 2A, a metal line 110 is disposed on the non-display area of TFT array substrate 100. The metal line 110 can be simultaneously formed with gate metal lines of the TFT array on the display area of substrate 100. An insulating layer 120 is then formed, covering the metal line 110 and the exposed surface of the substrate 100. Another metal line 130 is then formed on the insulating layer 120, close to the metal line 110. The metal line 130 can be simultaneously formed with source/drain metal lines of the TFT array on the display area of substrate 100. A second insulating layer 140 is formed, covering the metal line 130 and the insulating layer 120. Conventionally, the thicknesses of the metal lines 110 and 130 are about 2500 Å, and those of the insulating layer 120 and 140, 3000 Å, approximately. A thick passivation layer 150 is then formed on the surface of the insulating layer 140, with a thickness of 3-4 μm.
The thick passivation layer 150 is then patterned to form two passivation layers 151 and 152 as shown in FIG. 1, exposing a long strip of insulating layer 140 above where the metal lines 110 and 130 will be interconnected. The insulating layer 140 therebetween is further patterned to form two via holes 141 and 142, exposing the underlying metal lines 110 and 130 respectively, as shown in FIG. 2B.
An ITO (indium tin oxide) layer 160, of a conductive material, is then deposited on the surface of substrate 100, substantially filling via holes 141 and 142 to form wiring between metal lines 110 and 130. A thick photoresist layer 170 is then deposited over the surface of the ITO layer 160, at a thickness of about 1.5 μm in the central area of the ITO layer 160 between the two passivation layers 151 and 152. However, due to the thick passivation layers 151 and 152 and the fluidity of photoresist, the photoresist layer 170 on the ITO layer 160 at the foot of the passivation layers 151 and 152 may be as thick as 3 μm or more, as shown in FIG. 2C.
The photoresist layer 170 is then patterned to form a rectangular mask 172 covering the ITO layer 160 between the passivation layers 151 and 152, thereby exposing the rest of the ITO layer 160, as shown in FIG. 2D. However, the overly thick photoresist layer 170 at the foot of the passivation layers 151 and 152 may not be removed thoroughly, such that photoresist residue 170′ remains along the foot of the passivation layers 151 and 152, thereby covering two strips of ITO layer 160.
The uncovered ITO layer is then etched and removed using the patterned photoresist layer 172 as a mask. Due to the photoresist residue 170′ also covering the ITO layer 160 along the foot of the passivation layers 151 and 152, the ITO layers covered by the photoresist residue 170′ are not removed. After the photoresist mask 172 and residue 170′ are removed, an ITO wiring 162 is formed to connect the corresponding metal lines 110 and 130, as shown in FIG. 2E. In addition to the ITO wirings 162 for the connection of every set of corresponding metal lines 110 and 130, two strips of remnant ITO layers 160′ also form along the foot of the two passivation layers 151 and 152, as shown in FIG. 1. If the remnant ITO layer 160′ extends to contact the central ITO wiring 162, the parallel metal lines 110 and 130 nearby may all connect, resulting in a short circuit.